Introduction

The GIGACOM VSL320 PHY is a member of the Velocity™ Serial Link family of high-speed interface solutions. The VSL PHY family addresses many existing and emerging interface standards with scalable and silicon-efficient products. This comprehensive family of products covers a wide range of standards from 1.06 Gbps to 6.4 Gbps with the smallest footprints in the industry. The benefits of these highly integrated PHY solutions include differentiated performance, simplified interoperability and extensive built-in testability. GIGACOM minimizes risk with our silicon verification/interoperability program, resulting in highly reliable products which are manufacturable in leading CMOS processes.


Product Descriptions


The GIGACOM VSL320 PHY provides a comprehensive feature set and a well-defined architecture that allows designers extensive flexibility for various applications and a roadmap to future products.


The feature set for the GIGACOM VSL320 PHY includes:

  • Very low output jitter
  • Total output jitter at 3.125 Gbps is >50% improvement over XAUI specification
  • Receiver equalization for enhanced jitter tolerance
  • Receiver jitter tolerance at 3.125 Gbps is >20% improvement over XAUI specification
  • Programmable TX levels with multiple post-cursor emphasis options
  • Automatic driver/receiver impedance calibration
  • 8/10 bit interface or 16/20 bit interface
  • Signal detection
  • Power saving modes
  • Status pins for checking PHY functionality
  • Integrated bandgap
  • Very small size
  • Extensive built in testability
  • At-speed BIST circuitry with various PRBS and 8B10B patterns
  • Multiplexed scan for testability of all digital logic
  • Eye width mapping and on chip jitter generation capability
  • Loop back modes
  • Serial Control Register
  • Support for DC and AC JTAG (AC EXTEST)

The GIGACOM VSL320 PHY consists of one or more Lane Blocks that perform the parallel-to-serial and serial-to-parallel conversion for a physical layer interface, and a Common Block which provides clocks and bias. See the functional block diagram in Figure 2-1, which shows a four lane example of a VSL320 PHY. The user can choose to have from one to sixteen lanes in a single PHY.


Each transmit section of a Lane consists of an 8-, 10-, 16-, or 20-bit parallel interface, a serializer, a differential CML driver with selectable pre-emphasis and swing levels, and a BIST pattern generator.


Each receive section of a Lane consists of a differential CML receiver with equalization, clock and data recovery circuitry, signal detection, de-serializer, 8-, 10-, 16-, or 20-bit parallel interface, and BIST pattern verifier.


The Common Block generates all required bias currents, contains startup and auto calibration logic, and contains the PLL which multiplies the reference clock to the required Serial Link Rate(s) and provides the reference clock for each of the Clock/Data Recovery (CDR) units.


   

For a detailed Product Brief and presentation of the IP, please contact us at info@gigacomsemi.com

 
Write to Us: info@gigacomsemi.com