The Gigacom VSL312 PHY is suitable for both Root Complex and End Point applications within a PCI Express system. The VSL312 PHY provides a comprehensive feature set, a well-defined architecture that allows designers extensive flexibility for various applications, and a roadmap to future products. Additionally, the VSL312 PHY provides support for a number of PCI Express addendums and extensions including the Mobile Graphics Low Power addendum and the Wireless Form Factor extension.
The VSL312 PHY is comprised of a hardened GDSII Physical Medium Attachment (PMA) sub-layer containing the SerDes, plus a soft Physical Coding Sub-layer (PCS) Verilog module with a PHY Interface for the PCI Express (PIPE) that is connected to the hard macro at the PMA interface. The PIPE PCS, when coupled with the hardened PMA SerDes macro, provides a PCI Express PHY with PIPE compliant signals for the end customer. Since the VSL PHY family includes many test features and capabilities that are not part of the PIPE, additional pins from the PMA layer are also available.
The feature set for the Gigacom VSL312 PHY includes:
- PCI Express Gen 2 and Gen 1 compliant
- Supports 5.0 Gbps and 2.5 Gbps data rates
- Root Complex or End Point applications
- Root Complex supports Port Bifurcation factors of x1, x4, or x8
- Transmission jitter generation and receiver jitter tolerance which exceed PCI Express jitter specifications
- Electrical Idle signaling and detection
- Receiver detection
- 8B10B encode/decode, comma detection, clock compensation buffer, and symbol alignment
- Supports various PCI Express modes and extensions
- Power management (P0, P0s, P1, P2) and Low Signal Swing modes
- Clock Power Management
- Wireless Form Factor and ExpressCard
- Programmable amplitude and pre-emphasis
- Programmable receiver equalization
- PIPE v2.0 compliant signals
- Three different build configurations are supported for customer applications
- Fixed 8 or 16-bit datapath interface with dynamic PCLK rate in Gen1 and Gen2 speeds
- Constant Clock Mode with a fixed 250 MHz PCLK and variable 8/16 bit datapath interface at Gen1 and Gen2
- Reverse Clock Mode with an externally supplied 250 MHz PCLK and variable 8/16 bit datapath interface at Gen1 and Gen2
- Status pins for checking PHY functionality
- Integrated bandgap
- Automatic driver/receiver impedance calibration
- Very small size
- Extensive built in testability
- At-speed BIST circuitry with the PCI Express compliance pattern, plus various PRBS and 8B10B patterns
- Multiplexed scan for testability of all digital logic
- Eye width mapping and on-chip jitter generation capability
- Loop back modes
- Serial Control Register
- Support for DC and AC JTAG (AC EXTEST)
The Gigacom VSL312 PMA sublayer consists of one or more Lane Blocks that perform the parallel-to- serial and serial-to-parallel conversion for a physical layer interface, and a Common Block which provides clocks and bias. See the functional block diagram in Figure 2-1, which shows an example of a four lane PHY. The user can choose to have from one to sixteen lanes in a single PHY.
Each transmit section of a Lane with associated PIPE logic consists of an 8- or 16-bit parallel interface, an 8B10B encoder, a serializer, a differential CML driver with selectable PCI Express de-emphasis and swing levels, and a BIST pattern generator.
Each receive section of a Lane with associated PIPE logic consists of a differential CML receiver with equalization, clock and data recovery circuitry, signal detection, de-serializer, comma (K28.5) detection and word symbol alignment, 8B10B decoder, 8- or 16-bit parallel interface, elastic buffer and BIST pattern verifier.
The Common Block generates all required bias currents, contains startup and auto calibration logic, and contains the PLL which multiplies the reference clock to the required serial link rate and provides the reference clock for each of the Clock/Data Recovery (CDR) units.